SRAM voltage control for improved operational margins

ABSTRACT

A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

BACKGROUND OF THE INVENTION

The present invention relates to static random access memories(“SRAMs”), and more particularly to SRAMs having circuits for altering avoltage level supplied thereto. In addition, aspects of the inventionrelate to methods of operating an SRAM in which a voltage level suppliedthereto is altered.

SRAMs are uniquely suited to the functions they serve within processorsand other devices for storage of data to which fast (low cycle time) andready (low latency) access is desired. Certain types of storage withinprocessors are almost always implemented using SRAMs, such as cachememories, control stores, buffer memories, instruction pipelines anddata pipelines including input output interfaces and buffers for directmemory access (“DMA”) interfaces. In addition, certain storage used forcommunication interfaces, e.g., network adapter buffers and so on, alsoutilize SRAMs for speed and low latency. Since SRAMs are frequentlyincorporated into chips on which other functions are implemented, e.g.,processors (also referred to variously as microprocessors and centralprocessing units (“CPUs”)), they must perform at operating conditions asdifficult as those that the processors must tolerate. In particular,SRAMs must perform within the same broad range of operating temperaturesas processors and must be capable of tolerating fluctuations in supplyvoltages, e.g., noise disturbance, to the same extent as processors.Moreover, the sizes of SRAMs and SRAMs incorporated into chips havingother functions are increasing. It is not uncommon for SRAMs to storemany tens of millions of bits, even for SRAMs which are incorporatedinto other chips such as processors. In addition, to satisfy a growingdemand for application specific integrated circuits (“ASICs”), it isdesirable to provide SRAM macros (“macros” being functional modules)with large capacities capable of incorporation into multi-functionchips, despite the scaling of the transistors and voltages used thereinto unprecedented small sizes and values.

Storage cells in an SRAM or “SRAM cells” are arranged in an array ofSRAM cells or “SRAM array.” Wordlines (“WL”) run in a direction of rowsacross an SRAM array. Bitlines run in a direction of columns across theSRAM array. Typically, one wordline WL is connected to each cell of arow of cells in the SRAM array. Typically, two bitlines carryingcomplementary signals are connected to each cell in a column of cells inthe SRAM array, with one of the bitlines carrying a “true” signalrepresenting the actual state of a bit signal and the other bitlinescarrying a “complementary” signal representing an inverted version ofthe bit signal.

As the size of each cell within the SRAM array decreases with latergenerations of SRAMs, the threshold voltage of field effect transistors(“FETs”) used in each cell is subject to increased variability. Inaddition, the voltage level at which power is supplied to the SRAM arrayis reduced or “scaled” with the introduction of new generations ofSRAMs.

The increased variability of the threshold voltage of the FETs of cellsof an SRAM and the reduced power supply voltage level make it harder toguarantee that certain margins of error are maintained during operationof the SRAM. Such margins of error have a direct bearing on the SRAM'sability to maintain the integrity of the data stored therein. Clearly,there is a requirement that an extremely miniscule amount of such errorsoccur during operation of an SRAM. The maximum tolerable error or upperlimit for such error is often measured in terms of a number of “sigma”,sigma representing the standard deviation in a distribution curverepresenting the occurrence of such errors. As currently manufactured,SRAMs can have many millions of cells per SRAM array, the upper limittypically is set at one or two errors per the SRAM array. Stated anotherway, the maximum tolerable rate of error is set at a level such as oneor two parts per billion, for example. This translates approximately to5.2 sigma.

Margins of error which need to be maintained in the SRAM include accessdisturb margin (“ADM”) and write margin (“WRM”). The state of a bitstored in a cell of an SRAM is more likely to undergo a spontaneousinversion when the SRAM cell is partially selected. Access disturbmargin (ADM) is a measure of the likelihood that the state of a bitstored in a partially selected cell of the SRAM array will spontaneouslychange from one state to another, e.g., flip from a “high” to a “low”state when a cell of the SRAM is accessed during a read or writeoperation. An unselected SRAM cell is “half” selected when a wordlineconnected to that cell has been activated. In other words, a cell ishalf selected when another cell connected to the same wordline isaccessed for either a read or a write operation. Such “half” selectedcells are more susceptible to disturbance during access to the cellswithin the SRAM because such cells are frequently subject to potentialdisturbance during such accesses at times when they are not beingaccessed.

Another margin of error that must be satisfied is the ability to writethe state of bit to an SRAM cell, given the strength of the bitlinessignals supplied to the SRAM cell and the time allotted to do so. Here,it is important that the SRAM cell have sufficient drive current tochange from one stable state to another state under the influence of thebitlines signals supplied thereto. If the SRAM cell fails to be writtenwith the bit that is provided thereto, data integrity is impacted. WRMpertains to the occurrence of this type of error. Here again, it isimportant to reduce this type of error to an extremely miniscule amount.WRM, like ADM is typically measured in terms of standard deviations or“sigma” from a center of a distribution of the occurrence of error. Asin the above case, WRM should preferably be maintained at a high sigmanumber, preferably at a sigma value of about 5.2 or more.

The scaling of one or more voltages supplied to each SRAM cell of theSRAM array for each succeeding generation of SRAMs only increases thedifficulty of achieving a desired ADM and desired WRM. Variousapproaches have been suggested for providing high ADM, despite thescaling of the voltages. Increasing the threshold voltage of each n-typeFET (“NFET”) and p-type FET or (“PFET”) helps improve ADM. However, suchapproach potentially worsens WRM. In an SRAM, the available amount ofdrive current within each SRAM cell is already limited because of thescaling of the voltage. As a result, raising the threshold voltages ofthe NFET and PFET make the NFET weaker and the PFET stronger. While theSRAM cell becomes more stable under such conditions, writing each SRAMcell becomes more difficult than before.

Moreover, whether or not the threshold voltage of the NFETs is raised orthat of the PFETs is lowered, ADM and WRM tend to respond differently totemperature. The sigma value of ADM tends to be higher at lowertemperatures, e.g., when a chip containing an SRAM is first turned on orwhen the chip is running at lower frequency. On the other hand, thesigma value of ADM becomes lower with increasing temperature. On theother hand, the sigma value of WRM may be lower at lower temperatures,and the sigma value of the WRM may become higher with increasingtemperature. As transistor sizes are scaled further downward in futuregenerations of SRAMs, it becomes more difficult to achieve desirablesigma values on both ADM and WRM over the range of temperatures in whichSRAMs (and processors which incorporate them) are required to operate.

Providing write schemes for SRAM cells having PFET passgates is one goalfeatured in commonly assigned U.S. Pat. No. 6,549,453 to Wong (“the '453Patent”). In one scheme described in the '453 Patent, a voltage providedto a memory cell is adjusted from one level to another during a datawriting operation to the memory cell. Circuits are provided by which asupply voltage provided to pull-up devices of the memory cell “floatsdown” to a lower level during the data writing operation. In addition,in one or more other schemes described therein, pull-down devices of thememory cell are disconnected from ground and allowed to “float up” to avoltage level higher than ground.

From the foregoing discussion, it is clear that new ways are needed tomaintain high WRM and ADM in SRAMs despite further scaling of thetransistors and voltages used in SRAM cells.

SUMMARY OF THE INVENTION

According to embodiments of the invention described herein, write marginwithin the SRAM is improved by lowering the power supply voltageprovided to the column of SRAM cells to decrease the stability of thosecells and thus make them easier to write to a different state.Preferably, embodiments of the invention herein are implemented in alayout pattern referred to as “thin cell layout” in which each column ofthe SRAM cells is served by a separate conductor carrying a power supplyvoltage. In a thin cell layout, power supply conductors run along themiddle of columns of SRAM cells. In such case, the placement of thepower supply conductors in the middle of columns of SRAM cells allowsthe power supply voltage to individual columns to be lowered whileminimizing the effects upon cells in neighboring columns of the SRAM. Inparticular, the placement of power supply conductors in the middle ofthe columns reduces or minimizes the coupling of noise to the cells ofneighboring columns due to changes in the levels of the voltage suppliedto individual columns.

Embodiments of the invention described herein improve write marginwithout decreasing the stability of cells that are half-selected by anactivated wordline. Therefore, such half-selected (wordline-selected)cells are kept from being made vulnerable to access disturbance.

In addition, in one or more of the embodiments described below, an NFETis used to actively pull down the power supply voltage from the nominallevel Vdd to a lowered level Vdda, a process which in some instances canbe made to occur faster than simply allowing the power supply voltagelevel to float down to a certain level. In addition, timing ispreferably controlled so that the power supply voltage is reduced, andwrite values appear on the bitlines before the wordline is activated. Inthis way, maximum use is made of the limited duration duty cycle of thewordline. These things make it possible to scale the SRAM cell furtherwhile maintaining or increasing the sigma value. With higher sigmavalues of ADM and WRM, larger sizes of caches and buffers can beaccommodated without increasing the likelihood that an error will occur.

In accordance with one or more embodiments of the invention, an SRAM isprovided which includes NFETs as passgates of the cells therein. For thesame size and similar processes used to manufacture NFETs and PFETs,NFETs produce higher on-current than PFETs. This occurs because of thehigher mobility of electrons, the dominant charge carriers in NFETs, ascompared to the mobility of holes, the dominant charge carriers inPFETs. Therefore, when the size of NFETs and PFETs and theirmanufacturing processes are about the same NFET passgates permit theSRAM cell to be written more quickly than PFET passgates. Thus, for thesame size of an SRAM cell and the same ADM value, a higher WRM value isgenerally achieved using NFET passgates than when using PFET passgates.Conversely, for same WRM value and ADM value, smaller SRAM cell size canbe achieved using NFET passgates than can be achieved using PFETpassgates.

A static random access memory (“SRAM”) includes a plurality of SRAMcells arranged in an array, the array including a plurality of rows anda plurality of columns. The SRAM further includes a plurality ofbitlines, in which at least two bitlines correspond to each column ofthe plurality of columns of the array.

In one embodiment, a static random access memory (“SRAM”) includes aplurality of SRAM cells arranged in an array, the array including aplurality of rows and a plurality of columns. A plurality of voltagecontrol circuits correspond to respective ones of the plurality ofcolumns of the array, each of the plurality of voltage control circuitsbeing coupled to an output of a power supply. Each voltage controlcircuit has a function to temporarily reduce a power supply voltageprovided to a plurality of SRAM cells belonging to a selected column ofthe SRAM. Such column is selected during a write operation in which abit is written to one of the plurality of SRAM cells belonging to theselected column.

In one embodiment of the invention, the voltage control circuit includesa first p-type field effect transistor (“PFET”) and a second PFET, thesecond PFET having gate and drain terminals tied together, and eachvoltage control circuit further includes an n-type field effecttransistor (“NFET”) having a conduction path coupled between the drainterminals of the first and second PFETs and ground.

In a particular embodiment, the voltage control circuit includes ann-type field effect transistor (“NFET”) and a p-type field effecttransistor (“PFET”), each of the NFET and the PFET having a conductionpath connected to the output of the power supply.

In another embodiment, the voltage control circuit includes a firstp-type field effect transistor (“PFET”) and a second PFET, the secondPFET having gate and drain terminals tied together.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block and schematic diagram illustrating an SRAM inaccordance with an embodiment of the invention.

FIG. 2 is a schematic diagram further illustrating an SRAM in accordancewith a particular embodiment of the invention.

FIGS. 3( a) through 3(d) are timing diagrams illustrating operation ofan SRAM in accordance with an embodiment of the invention.

FIG. 4 is a schematic diagram illustrating an alternative voltagecontrol circuit in accordance with a variation of the embodimentillustrated in FIG. 1.

FIG. 5 is a schematic diagram illustrating a further alternative voltagecontrol circuit in accordance with another variation of the embodimentillustrated in FIG. 1.

DETAILED DESCRIPTION

FIG. 1 is a block and schematic diagram illustrating an SRAM 100 inaccordance with an embodiment of the invention. The SRAM 100 can be astand-alone SRAM on a dedicated chip containing only one or more suchSRAMs 100, or be incorporated into a chip having one or more additionalfunctions, such as incorporated into a chip on which a processor ornetwork interface is provided, for example.

As illustrated in FIG. 1, the SRAM includes a plurality of storage cells110, each storage cell operable to store a data bit and to provide readaccess and write access thereto when power is supplied to the SRAM 100during normal operation. The SRAM 100 typically includes many suchcells, ranging from several thousand cells per SRAM to many millions ofcells. Within the SRAM, storage cells are arranged in an array having aplurality of columns 102, 104, 106, etc., a plurality of rows 112, 114,116, etc. For ease of illustration, only a few such cells 110 are shown.

The bitlines of the SRAM are arranged in a direction of the columns, twocomplementary bitlines BL and /BL being provided per each column of thearray. One bitlines (BL) is a “true” bitlines which carries a signalrepresenting the true or actual value of the data bit that is read fromor written to one of the SRAM cells 110 coupled to that bitlines. Theother bitlines (/BL) carries a signal representing the complement of thevalue of the data bit that is read from or written to one of the SRAMcells 110 coupled to that bitlines. The wordlines WL of the SRAM arearranged in a direction of the rows, one wordline being provided foreach row. The wordlines WL operate to provide read and write access tocells coupled to each wordline in a row of the SRAM.

Greatly simplified, the reading of data to the SRAM and writing of datafrom the SRAM is performed by changing the voltage of the wordline WLfrom an inactive level to an active level to provide access a row ofcells within the SRAM, e.g., row 112. Then, when the operation is toread data stored in the SRAM, a data bit stored in one of the cells ofthe accessed row is transmitted as a signal along the complementary pairof bitlines BL, /BL coupled to the cell to the data input output (“I/O”)unit 120 coupled to the pair of bitlines. When the operation is to writedata to the SRAM, a data bit is transmitted as a signal from the dataI/O unit 120 in a direction of an accessed column of cells along thecomplementary pair of bitlines BL, /BL to one of the cells that alsobelongs to the row of cells accessed by the wordline WL.

During a read operation, when the signal arrives at the data I/O unit120, it usually is a small swing signal having a value, e.g., 15 to 30millivolts (mV) which varies little from when the signal is inactive towhen it is active. Illustratively, a sense amplifier in the data I/Ounit 120 amplifies the small swing signal arriving thereto from theaccessed cell to a rail-to-rail signal, i.e., one which has either anormal high logic level or a normal low logic level. In CMOStechnologies of interest at the time of this application, a rail-to-railsignal swings from a high logic level of about 1 volt to a low logiclevel of ground. However, the embodiments of the invention herein areusable in SRAMs which have smaller or larger rail-to-rail signal swingsthan the 1 volt to ground example of a signal swing that is discussedhere. In addition, while the low logic level is frequently set atground, SRAMs exist in which the low logic level is set at a voltageother than ground. Unless otherwise specified, it is intended by way ofthe examples and embodiments described herein not to limit the nominalhigh and low logic levels used within the SRAM to any particularvoltages or ranges of voltage.

During a write operation, a particular column of the SRAM is selected tobe written through column select circuitry 130, as driven by columnaddressing signals provided thereto (not shown). Prior to performing thewrite operation, the voltage levels on both bitlines BL and /BL are setto the high logic level. During the write operation, typically thevoltage on one of the bitlines BL and /BL of a column is lowered fromthe high logic level to the low logic level. Typically, a data bit valueof zero is represented by a voltage of ground and a data bit value ofone is represented by the high logic level, being illustratively 1 volt.Thus, illustratively, when a data bit value of zero is to be written,the voltage on the true bitlines BL is lowered to ground. Conversely,when a data bit value of one is to be written, the voltage on thecomplementary bitlines /BL is lowered to ground. An operation to writethe SRAM cell is thus a process driven by the ground voltage level onone of the pair of bitlines.

As further shown in FIG. 1, the SRAM includes a voltage control unit140, preferably occurring at a rate of one unit per column. The voltagecontrol unit 140 raises and lowers the power supply voltage Vs(t) toeach SRAM cell within a particular column as a function of time topermit a cell belonging such column to be written more easily. Thevoltage control unit 140 controls the level of the power supply voltageVs(t) between a nominal level Vdd and a lowered level Vdda. The nominallevel Vdd is a level at which power is normally provided to cells withinthe SRAM during read operations and to columns within the SRAM wheneverthose columns are not being written to at a particular time. The loweredlevel Vdda is a level at which power is provided to cells in aparticular column of the SRAM when a cell belonging to such column isbeing written. Ordinarily, the lowered level Vdda will above 50% of theVdd level. As a boundary condition, the lowered level Vdda should be atleast slightly higher than the threshold voltage level of the NFETtransistor in a cell of the SRAM. Preferably, the lowered level Vdda isa level of about 70% to 80% of the nominal level Vdd. As an illustrativeexample, when Vdd is about 1 volt, the lowered level Vdda can be a levelsuch as 0.7 volt. In an exemplary embodiment, Vdda is lower than Vdd byan amount equal to the threshold voltage of a transistor used to varythe power supply voltage Vs(t) between the two levels.

When the power supply voltage Vs(t) is at the nominal level Vdd, greaterprotection is provided against the possibility of access disturbance,the above-described problem of spontaneous change in a stored bit value.However, the temporary reduction in the power supply voltage Vs(t) tothe lowered level Vdda permits a cell of the accessed column of SRAMcells to be written more easily. This increases one's ability to writeto the SRAM and improves write margin within the SRAM.

As further shown in FIG. 1, preferably, each column of the SRAM cells isserved by a separate conductor 150 carrying a power supply voltage in alayout pattern referred to as “thin cell layout.” In such layout, powersupply conductors run along the middle of columns of SRAM cells. Theplacement of the power supply conductors in the middle of columns ofSRAM cells allows the power supply voltage to individual columns to belowered while minimizing the effects upon cells in neighboring columnsof the SRAM. In particular, the placement of power supply conductors inthe middle of the columns reduces or minimizes the coupling of noise tothe cells of neighboring columns due to changes in the levels of thevoltage supplied to individual columns.

FIG. 2 is a schematic diagram further illustrating an SRAM 200 accordingto a particular embodiment of the invention. The SRAM 200 is aparticular example of the SRAM 100 described above with reference toFIG. 1 and operates in a manner like that of SRAM 100 described above.The structure and operation of SRAM 200 are described herein only to theextent as more particularly shown in FIG. 2 in relation to SRAM 100. Asshown in FIG. 2, the SRAM 200 includes a plurality of individual storagecells 210. As above, only a few of the storage cells of the SRAM areshown in FIG. 2 for ease of illustration. Each storage cell, for examplecell 210 a, includes a latch and passgates. The latch includes a pair ofcross-coupled inverters including a first inverter formed by PFET P1 andNFET N1, and a second inverter formed by PFET P2 and NFET N2. In eachlatch, the gate inputs of each inverter are connected to the commondrain terminal of the other one of each inverter shown. In theparticular example shown in FIG. 2, cell 210 a and other cells 210 ofthe SRAM each include a pair of passgates implemented by NFETs N3 andN4.

Passgates N3 and N4 are activated by a high logic level voltage providedto the gate inputs of N3 and N4. When activated, the passgates N3 and N4permit a bit to be read from or stored to a cell 210. Specifically, whenactivated, during a read operation the passgates couple bit signals froma cell 210 onto bitlines BL and /BL to be read by data I/O circuitry(FIG. 1). In addition, during a write operation, the passgates couplebit signals driven on bitlines BL and /BL by the data I/O circuitry to acell 210 to write a data bit the cell 210.

The SRAM 200 further includes voltage control circuitry 240, preferablyhaving a structure as shown particularly in FIG. 2. Preferably, thevoltage control circuitry for each column of the SRAM 200 includes afirst PFET P5, a second PFET P6 and an NFET N5. The gates of PFET P5 andNFET N5 are tied together and the drains of PFET P5 and NFET N5 are tiedtogether as a common drain terminal. The gate and drain of PFET P6 aretied together so as to operate PFET P6 as a diode. The drain of PFET P6is further tied to the common drain terminal of PFET P5 and NFET N5. Awrite bit select signal, e.g., signal WR_BIT_SEL2 is applied to thegates of PFET P5 and NFET N5.

Operation of the voltage control circuit 240 is as follows. During aread operation or during operation in which the SRAM is neither readfrom nor written to, the write bit select signals WR_BIT_SEL0,WR_BIT_SEL1, and WR_BIT_SEL2 are maintained at the low logic level, suchas ground. One of these signals WR_BIT_SEL2 is applied to the gate ofPFET P5 of the voltage control circuit 240 a. This has the effect offully turning on P5. At that time, the full power supply voltage levelVdd is passed through P5 from the power supply Vdd to the drain of P5.At such time, the full power supply voltage level Vdd also appears atthe gate of PFET P6, such that P6 is turned off. In such case, the fullpower supply voltage level Vdd is passed through to cells of the column202 served by the voltage control circuit 240 a.

On the other hand, during a write operation, the write bit select signalWR_BIT_SEL2 to the voltage control circuit 240 a is at a high logiclevel, having a high voltage signal above the threshold voltage of NFETN5. The high logic level of the write bit select signal is also abovethe threshold voltage of PFET P5, such that P5 is turned off at thattime. At that time, NFET N5 and PFET P6 are also turned on. N5 functionsas a pull-down device having an effect of quickly lowering the voltageat its drain from the Vdd level to a lower level. With the signalWR_BIT_SEL2 being high, P6 functions in a manner similar to a diode,producing a voltage drop approximately equivalent to its thresholdvoltage as a PFET.

The use of N5 as a pull-down device assures that the voltage controlcircuit 240 a and other like voltage control circuits 240 transition thepower supply voltage quickly when the voltage control circuit isselected by a write bit select signal at the high logic level. Thepull-down device actively pulls down the power supply voltage Vs(t)present at the drain of N5 from Vdd to the lower Vdda level. In fact, ingeneral, the circuit 240 a transitions the power supply voltage from thenominal level Vdd to the lower level Vdda faster than in a circuit whichhas no such pull-down device connected to transistors P5 and P6. Bylowering the power supply voltage Vs(t) quickly from Vdd to the lowerlevel upon arrival of the WR_BIT_SEL2 signal, the circuit 240 appliesthe lower level of the power supply voltage Vs(t) at an earlier point intime to the cells of column 202. The lowered power supply voltage levelVs(t) and its early application to the cells of column 202 assure that awrite operation to one of the cells along that column 202 is performedas early within the duty cycle of the write operation as possible.

FIGS. 3( a) through 3(d) are timing diagrams illustrating signals duringa write operation to a cell 210 a of an SRAM 200 according to theembodiment of the invention illustrated in FIG. 2. Signals are timedsuch that the power supply voltage Vs(t) is lowered to the accessedcolumn prior to the activation of the wordline WL, thus assuring thatconditions are at their most favorable for writing the cell beginningfrom the time that the wordline is activated. Some of the signals shownin FIGS. 3( a) through 3(d) transition at signal edges that coincidetogether, as described below. The time intervals shown in FIGS. 3( a)through 3(d) are illustrative of the duty cycles of the signals inrelation to each other. In the illustrative example shown in FIGS. 3( a)through 3(d), the cycle time for performing one write access to the SRAMis 1000 picoseconds (“ps”), i.e., 1 nanosecond (“ns”),

Operation of the SRAM in accordance will now be explained with referenceto the signals shown in FIGS. 3( a) through 3(d). FIG. 3( a) illustratesa write bit select signal WR_BIT_SELn. This signal activates one of thevoltage control circuits 240 shown in FIG. 2, for example, the voltagecontrol circuit 240 a to lower the power supply voltage Vs(t) to aselected column of the SRAM. This signal is also used to select andactivate one bitlines (i.e., lower the voltage thereon to ground) of thepair of complementary bitlines of the selected column.

As seen in FIG. 3( b), the power supply voltage Vs(t) input to thecolumn of SRAM cells falls from the higher steady-state level Vdd valueto the lowered level Vdda in synchronism with the rise in the signalWR_BIT_SELn input to the voltage control circuit 240. At such time, NFETN5 of the voltage control circuit 240 a (FIG. 2) actively pulls down thepower supply voltage from Vdd to the lowered level Vdda, such levelbeing determined by the threshold voltage of PFET P6 which is connectedto function as a diode within the circuit 240 a. In such manner, thepower supply voltage Vs(t) readies the cell for writing when WR_BIT_SELntransitions from ground to the high Vdd level. In addition, referring toFIG. 3( c), in preparation for writing the data bit to the cell, thevoltage level on one bitlines of the pair of bitlines BL, /BL is alsolowered from Vdd to ground at or about the same time that WR_BIT_SELnrises from ground to Vdd.

After the foregoing transitions have occurred: i.e., WR_BIT_SELn havingtransitioned to the active state, e.g., from ground to Vdd, the bitlinessignals adjusted to a value for writing a data bit to the cell, and thepower supply voltage Vs(t) having been lowered to the lowered levelVdda, the wordline is activated. Conventionally, it is sought toincrease the duty cycle of a wordline to be as long as possible withinthe cycle time for writing a data bit to a cell of the SRAM. This isdone to allow time for signal current to flow between the cell throughpassgates of the cell to or from the bitlines, causing the latch of thecell to flip from one state to the other.

However, the state of a data bit stored in one cell of the SRAM cannotchange until other conditions favor its immediate change. Here,conditions are not at their most favorable for changing the state of abit stored in the SRAM until the power supply voltage level Vs(t) hasfallen to the lowered level Vdda from the nominal level. In recognitionthereof, in the embodiment of the invention illustrated in FIGS. 2 and3( a) through 3(d), the duty cycle of the WR_BIT_SELn, the loweredvoltage level Vdda, and the bitlines write values are extended as longas possible. Then, the wordline is activated at the earliest time atwhich the foregoing signals can be considered to reach stable statesfollowing their transitions. In the particular example shown in FIGS. 3(a) through 3(d), the wordline is activated at a time of approximately 50to 100 ps later, i.e., at a point in time which is approximately 5 to10% of the cycle time later than the time at which the power supplyvoltage level Vs(t) and the bitlines begin to transition to their writevalues. In such manner, the wordline is activated at a time when it ismost favorable to write a new data bit value to the accessed cell.

After the wordline is activated, it remains active for a period of timesuch as 500 ps, such duty cycle preferably being the maximum duty cyclepermitted within the period of one writing cycle of the SRAM. Inaddition, such duty cycle is selected to assure that the power supplyvoltage Vs(t) has reached the lowered level Vdd and the signals on thebitlines are stable or at least near stable state. After the wordline isactivated, current flows through the passgates of the cell between thecell and the bitlines coupled to the cell. Depending upon the value ofthe bit that was last previously stored in the cell and the value of thedata bit being written, the state of the SRAM either stays the same orflips from the one state to the other state, i.e., from zero to one, orfrom one to zero.

Thereafter, the after the bit has been written to the cell, the wordlineis deactivated again. The write bit select signal WR_BIT_SELn returns toground and the bitlines signals are both restored to Vdd. The powersupply voltage Vs(t) also returns to Vdd. Referring to FIG. 3( c), aprecharge/restore interval (“RESTORE”) then occurs.

Following the precharge/restore interval, when a cell is selected to bewritten again, a write bit select signal WR_BIT_SELn for the selectedcolumn is activated again, at which time the operations of lowering thepower supply voltage Vs(t), lowering the voltage on one of the bitlinesto a column occur, after which a wordline for a selected row isactivated to write the data bit to the selected cell.

In a variation of the embodiment described with reference to FIGS. 3( a)through 3(d), logic circuitry may be employed to enhance the reliabilityof writing to cells of the SRAM when the SRAM is to be writtencontinuously with data for a period of time extending over a pluralityof cycles. As an example thereof, when data is to be written to adefined subset of the columns of the SRAM, WR_BIT_SELn is raised fromground to Vdd for the subset of columns and the power supply voltageVs(t) is lowered for that subset of columns such that each of thecolumns is ready and primed to be written at that time. These signalsare then left steady, unchanging at these active states for the wholetime and for the number of cycles in which writing is performedcontinuously to the SRAM. Signals on bitlines are then altered in eachcycle to write values, but only for the columns of the SRAM that arebeing written in each cycle. Corresponding wordlines of the SRAM arealso activated in each cycle for the cells to be written in each cycle.Here, by leaving the write bit select signals and power supply voltagesVs(t) steady that are provided to each of many columns being writtenover a series of cycles, the power supply voltage has a greater measureof stability at the lowered level to such columns. In addition, asavings in current can be achieved for SRAMs in which the same column isaccessed during multiple cycles having avoided transitioning the powersupply voltage Vs(t) line to each column two or more times during theperiod that the SRAM is continuously written.

FIG. 4 illustrates a variation of the embodiment described above withreference to FIG. 2. As shown in FIG. 4, the voltage control circuit 340includes an NFET N7 and PFET P7 connected in parallel, having an upperconductive terminal in which the drain of N7 and the source of P7 areconnected directly to Vdd. The voltage control circuit 340 also has alower conductive terminal connected to the source of N7 and the drain ofP7 as the power supply voltage Vs(t) output from the voltage controlcircuit, such voltage being supplied to cells of a column of the SRAM.The write bit select signal WR_BIT_SELn is supplied in parallel to thegates of NFET N7 and PFET P7. In operation, when WR_BIT_SELn is at thedeselected state of ground, N7 is turned off and P7 is turned on. Atanother time, when WR_BIT_SELn is at the selected state of Vdd, N7 isturned on and P7 is turned off. At such time, the lowered level Vdda ofthe power supply voltage Vs(t) is lower than the nominal level Vdd bythe value of the threshold voltage of NFET N7.

FIG. 5 illustrates another variation of the embodiment described abovewith reference to FIG. 2. As shown in FIG. 5, the voltage controlcircuit 440 includes a first PFET P8 and a second PFET P9 connected inparallel, in which the sources of P8 and P9 are connected directly toVdd. The voltage control circuit 440 also has a lower conductiveterminal connected to the drains of P8 and P9 as the power supplyvoltage Vs(t) output from the voltage control circuit, such voltagebeing supplied to cells of a column of the SRAM. In circuit 440, thewrite bit select signal WR_BIT_SELn is supplied to the gate of PFET P8.The gate of PFET P9 is connected to its drain such that P9 operates as adiode when it is biased in a turned on state. In operation, whenWR_BIT_SELn is at the deselected state of ground, P8 is turned on and P9is biased in the off state such that Vdd is passed through P8 as thepower supply voltage Vs(t). At another time, when WR_BIT_SELn is at theselected state of Vdd, P8 is turned off. At that time P9 is turned onbut operates as a diode such that the voltage at the drain of P9 islower than Vdd by the threshold voltage of P9. At such time, the powersupply voltage Vs(t) has the lowered level Vdda, lower than the nominallevel Vdd by the value of the threshold voltage of P9.

By the foregoing embodiments, ways are provided to improve write margin(WRM) within an SRAM or other like memory without adversely affectingaccess disturb margin (ADM). Moreover, ways are provided to lower thepower supply voltage to cells of the SRAM and then time the activationof the wordline for the greatest success in writing the SRAM within thelimited cycle time of the SRAM.

While the invention has been described in accordance with certainpreferred embodiments thereof, many modifications and enhancements canbe made thereto without departing from the true scope and spirit of theinvention, which is limited only by the claims appended below.

1. A static random access memory (“SRAM”), comprising: a plurality ofSRAM cells arranged in an array, said array including a plurality ofrows and a plurality of columns; and a plurality of voltage controlcircuits corresponding to respective ones of said plurality of columnsof said array, each of said plurality of voltage control circuitscoupled to an output of a power supply, each said voltage controlcircuit being operable to temporarily reduce a voltage provided to powersupply inputs of a plurality of SRAM cells belonging to a selectedcolumn of said plurality of columns, said selected column being selectedduring a write operation in which a bit is written to one of saidplurality of SRAM cells belonging to said selected column, wherein eachsaid voltage control circuit includes an n-type field effect transistor(“NFET”) and a p-type field effect transistor (“PFET”), each of saidNFET and said PFET having a conduction path connected between the outputof the power supply and said power supply inputs of said plurality ofSRAM cells.
 2. The SRAM as claimed in claim 1, further comprising aplurality of power supply conductors, each running along a middle of arespective one of said plurality of columns of said array, each of saidplurality of power supply conductors connecting one of said plurality ofvoltage control circuits to said power supply inputs of said pluralityof cells of an individual one of said plurality of columns.
 3. The SRAMas claimed in claim 1, wherein, when data is written to one or more ofthe plurality of SRAM cells belonging to said selected column duringeach of a plurality of succeeding cycles, the voltage control circuitcorresponding to said selected column is operable to maintain thereduced voltage continuously over the plurality of succeeding cycles. 4.A method of controlling a voltage level supplied to a static randomaccess memory (“SRAM”), comprising: supplying a voltage to a pluralityof SRAM cells of the SRAM at a first voltage level unless the pluralityof SRAM cells belong to a column of a plurality of columns of the SRAMwhich is selected for a write operation; selecting a first column of theplurality of columns for a write operation; operating a first p-typefield effect transistor (“PFET”) and a second PFET to supply the voltageat a second voltage level lower than the first voltage level to aplurality of SRAM cells belonging to the first column, each of the firstand second PFETs having a conduction path connected between a powersupply and power supply inputs of the plurality of SRAM cells; whilecontinuing to supply the voltage at the second voltage level, writing abit to one of the plurality of SRAM cells belonging to the first columnduring a first write cycle; when the first column is no longer selectedfor write operations, operating the first and second PFETs to supply thevoltage at the first voltage level to the plurality of SRAM cellsbelonging to the first column.
 5. The method as claimed in claim 4,wherein the voltage supplied to the plurality of SRAM cells is suppliedto power supply inputs of the plurality of SRAM cells.
 6. The method asclaimed in claim 5, wherein the second voltage level is lower than thefirst voltage level by an amount equal to a threshold voltage of a fieldeffect transistor (“FET”).
 7. The method as claimed in claim 5, whereinthe second voltage level is lower than the first voltage level by anamount equal to the threshold voltage of an n-type FET (“NFET”).
 8. Themethod as claimed in claim 5, wherein the second voltage level is lowerthan the first voltage level by an amount equal to the threshold voltageof a p-type FET (“PFET”).
 9. The method as claimed in claim 5, whereinthe plurality of SRAM cells include passgates, the passgates includingNFETs.
 10. The method as claimed in claim 5, wherein the voltagesupplied to the plurality of SRAM cells is lowered to the second voltageat a first point in time and a wordline connected to an accessed one ofthe plurality of SRAM cells is activated at a second point in time laterthan the first point in time, the data bit being written to the accessedone of the plurality of SRAM cells after the second point in time. 11.The method as claimed in claim 4, wherein the firs and second PFETs havedrain terminal coupled to the power supply inputs of the plurality ofSRAM cells, wherein the step of operating the first and second PFETs tosupply the voltage at the second level includes operating an n-typefield effect transistor (“NFET”) having a conduction path coupled to thedrain terminals of the first and second PFETs to actively pull down thevoltage at the power supply inputs of the plurality of SRAM cells.
 12. Astatic random access memory (“SRAM”), comprising a plurality of cellsarranged in an SRAM having a plurality of columns; and a voltage controlcircuit operable to temporarily reduce a voltage provided to powersupply inputs of cells belonging to a selected column of said SRAM, saidselected column being selected during a write operation in which a bitis written to one of said cells belonging to said selected column,wherein said voltage control circuit includes a first p-type filedeffect transistor (“PFET”) and a second PFET, each of said first andsecond PFETs having a conduction path connected between a power supplyand said power supply inputs of said cells belonging to said selectedcolumn.
 13. An SRAM as claimed in claim 12, wherein gate and drainterminals of said second PFET are tied together.
 14. The SRAM as claimedin claim 12, wherein said voltage control circuitry further includes ann-type field effect transistor (“NFET”) having a conduction path coupledto said drain terminals of said first and second PFETs for activelypulling down said voltage supplied to said cells belonging to saidselected column.
 15. A method of controlling a voltage level supplied toa static random access memory (“SRAM”), comprising: supplying a voltageto cells of the SRAM at a first voltage level, the SRAM having aplurality of columns; selecting a column of the plurality of columns fora write operation; operating an n-type field effect transistor (“NFET”)and a p-type field effect transistor (“PFET”) to supply the voltage at asecond voltage level lower than the first voltage level to cells of theSRAM belonging to the selected column, each of the NFET and PFET havinga conduction path connected between an output of a power supply and apower supply input of the plurality of SRAM cells; while continuing tosupply the voltage at the second voltage level, writing a bit to one ofthe cells belonging to the selected column; and thereafter operating theNFET and the PFET to supply the voltage to the cells belonging to theselected column at the first voltage level again.